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29 de abr. de 2024 · Mon, 29 Apr 2024 14:02:16 +0100. share. This patch series enables the HSI2 (high speed interfaces) for gs101: - HSI2 feeds PCIe and UFS. The parts added here have been verified to work OK without the. clk_ignore_unused kernel command line option. Signed-off-by: André Draszik <andre.draszik@linaro.org>.
30 de abr. de 2024 · From: André Draszik <> Date: Tue, 30 Apr 2024 10:49:46 +0100: Subject [PATCH v2 1/4] arm64: dts: exynos: gs101: specify bus clock for pinctrl (far) alive
30 de abr. de 2024 · From: André Draszik <> Date: Tue, 30 Apr 2024 10:49:47 +0100: Subject [PATCH v2 2/4] arm64: dts: exynos: gs101: specify bus clock for pinctrl_peric[01]
29 de abr. de 2024 · HSI stands for High Speed Interface and as such it generates. clocks for PCIe, UFS and MMC card. This patch adds support for the muxes, dividers, and gates in. cmu_hsi2. The following clocks are marked CLK_IS_CRITICAL as disabling. them results in an immediate system hang. CLK_GOUT_HSI2_HSI2_CMU_HSI2_PCLK.
1 de may. de 2024 · While commit 255ec3879dd4 ("phy: exynos5-usbdrd: Add 26MHz ref clk support") correctly states that CLKRSTCTRL[7:5] doesn't need to be set on modern Exynos platforms, SSPPLLCTL[2:0] should be programmed with
1 de may. de 2024 · Some Exynos based SoCs like Tensor gs101 protect the PMU registers for security hardening reasons so that they are only write accessible in EL3 via an SMC call.
7 de may. de 2024 · From: André Draszik <> Subject [PATCH 0/5] a few fixes for the Samsung USB phy driver: Date: Tue, 07 May 2024 15:14:43 +0100
