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1 de may. de 2024 · Some Exynos based SoCs like Tensor gs101 protect the PMU registers for security hardening reasons so that they are only write accessible in EL3 via an SMC call.
23 de abr. de 2024 · The Exynos-based Google Tensor gs101 SoC has a DWC3 compatible USB controller and can reuse the existing Exynos glue. Update the dt schema to include the google,gs101-dwusb3 compatible for it.
29 de abr. de 2024 · These patches enable USB in peripheral mode on Pixel 6. We can only support peripheral mode at this stage, as the MAX77759 TCPCI. controller used on Pixel 6 to do the role selection doesn't have a(n. upstream) Linux driver. Therefore the role is defaulted to peripheral. without any endpoints / ports.
26 de abr. de 2024 · Chef Jos%c3%a9 Andr%c3%a9s honored seven World Central Kitchen aid workers killed in an Israeli airstrike in Gaza earlier this month.
1 de may. de 2024 · From: André Draszik <> Date: Wed, 01 May 2024 10:19:38 +0100: Subject [PATCH v2 3/7] phy: exynos5-usbdrd: support isolating HS and SS ports independently
23 de abr. de 2024 · While commit 255ec3879dd4 ("phy: exynos5-usbdrd: Add 26MHz ref clk support") correctly states that CLKRSTCTRL[7:5] doesn't need to be set on modern Exynos platforms, SSPPLLCTL[2:0] should be programmed with
30 de abr. de 2024 · From: André Draszik <> Date: Tue, 30 Apr 2024 10:49:49 +0100: Subject [PATCH v2 4/4] arm64: dts: exynos: gs101: specify empty clocks for remaining pinctrl
